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document number: mc33790 rev 10.0, 12/2006 freescale semiconductor advance information * this document contains certain information on a new product. specifications and information herein are subject to change without notice. ? freescale semiconductor, in c., 2006. all rights reserved. two-channel distributed system interface (dsi) physical interface device the 33790 is a dual channel physical layer interface ic for the distributed system interface (dsi ) bus. it is designed to meet automotive requirements. it can also be used in non automotive applications. it supports bidirectional communication between slave and master ics. some slave devices derive a regulated 5.0 v from the bus, which can be used to power sensors, thereby eliminating the need for additional circuitry and wiring. features ? two independent dsi compatible buses ? pinout matched to mc68hc55 (spi to dsi logic) ? wave-shaped bus output voltage ? independent thermal shutdown and current limit ? return signalling current detection ? internal logic input pull ups and pull downs ? on-board charge pump ?2.0 kv esd capability ? communications rate up to 150 kbps ? pb-free packaging designated by suffix code eg figure 1. 33790 simplified application diagram distributed system interface (dsi) dw suffix eg suffix (pb-free) 98asb42567b 16-pin soicw 33790 dsi0f dsi0s dsi0r dsi1f dsi1s dsi1r cpcap vdd gnd dsi0o vsup dsi1o gnd mc68hc55 33790 +5.0 v +25 v bus_in bus_out bus_in bus_out 33793 33793 33793 dsi slave device protocol converter mcu ordering information device temperature range (t a ) package mc33790dw / r2 -40 c to 85 c 16 soicw MCZ33790eg / r2
analog integrated circuit device data 2 freescale semiconductor 33790 internal block diagram internal block diagram figure 2. 33790 simplifi ed internal block diagram internal bias dsi bus cpcap wave- shaper charge pump bus supply voltage bus current sense + vsup (idle level) vdd (+5.0 v) dsi0f dsi0s dsi0r dsi0o dsi bus wave- shaper bus current sense + dsi1f dsi1s dsi1r dsi1o gnd transmitter driver transmitter driver
analog integrated circuit device data freescale semiconductor 3 33790 pin connections pin connections figure 3. 33790 pin connections table 1. 33790 pin definitions a functional description of each pin can be found in the functional pin description section beginning on page 8 . pin number pin name definition 1 dsi0f this logic input controls the frame output for dsi channel 0 in accordance with table 5 , page 8 . 2 dsi0s this logic input controls the signalling out put for dsi channel 0 in accordance with table 5 , page 8 . 3 dsi0r this logic output provides the return data for dsi channel 0 in accordance with table 5 , page 8 . 4 dsi1f this logic input controls the frame output for dsi channel 1 in accordance with table 5 , page 8 . 5 dsi1s this logic input controls the signalling out put for dsi channel 1 in accordance with table 5 , page 8 . 6 dsi1r this logic output provides the return data for dsi channel 1 in accordance with table 5 , page 8 . 7 nc unused. 8 cpcap used to store and filter charge pump output. 9 nc unused. 10 nc unused. 11 gnd circuit and bus ground return. 12 dsi1o dsi bus 1 input / output. 13 vsup idle level supply input. the voltage supplied to this pin sets the idle level on the dsi bus. 14 dsi0o dsi bus 0 input / output. 15 gnd circuit and bus ground return. 16 vdd 5.0 v logic supply input. dsi0f dsi0r dsi1f dsi1s dsi1r nc cpcap dsi0s vdd gnd dsi0o vsup dsi10 gnd nc nc 2 3 4 5 6 7 8 16 14 13 12 11 10 15 9 1
analog integrated circuit device data 4 freescale semiconductor 33790 electrical characteristics maximum ratings electrical characteristics maximum ratings table 2. maximum ratings all voltages are with respect to ground unless otherwise no ted. exceeding these ratings may cause a malfunction or permanent damage to the device. ratings symbol value unit electrical ratings supply voltage continuous load dump - t < 300 ms v sup v sup ( t ) - 0.5 to 25 40 v maximum voltage on input / output pins v dd dsixs, dsixf (1) dsixo (1) - 0.3 to 5.5 - 0.3 to v dd + 0.3 - 0.3 to v sup + 0.3 v storage temperature t stg - 55 to 150 c operating ambient temperature t a -40 to 85 c operating junction temperature t j - 40 to 150 c peak package reflow temperature during reflow (2) , (3) t pprt note 3 c continuous current per pin v dd dsixr v sup 0 to 10 - 2.5 to 5.0 500 ma thermal resistance junction to ambient r ja 45 c / w thermal shutdown t sd 155 to 190 c esd voltage (all pins) (4) human body model machine model v esd1 v esd2 2000 200 v notes 1. r = 0 ?. 2. pin soldering temperature limit is for 10 seconds maximum duration. not designed fo r immersion soldering. exceeding these lim its may cause malfunction or permanent damage to the device. 3. freescale?s package reflow capability m eets pb-free requirements for jedec standard j-std-020c. for peak package reflow temperature and moisture sensitivity levels (msl), go to www.freescale.com, search by part number [e.g. remove pref ixes/suffixes and enter the core id to view all orderable parts . (i.e. mc33xxxd enter 33xxx), and review parametrics. 4. esd1 performed in accordance with the human body model (c zap = 100pf, r zap = 1500 ? ), esd2 performed in accordance with the machine model (c zap = 200 pf, r zap = 0 ? ).
analog integrated circuit device data freescale semiconductor 5 33790 electrical characteristics static electrical characteristics static electrical characteristics table 3. static electric al characteristics characteristics noted under conditions 4.75 v v dd 5.25 v, 8.0 v v sup 25.0 v, -40 c t j 150 c unless otherwise noted. characteristic symbol min typ max unit supply i sup supply current / channel (not including i out ) dsix0 = idle voltage, -100 ma i out 0 ma dsix0 = output high voltage, i out = 12 ma i supi i suph ? ? 1.35 5.0 3.25 9.00 ma i dd supply current / channel i dd ? 0.5 1.0 ma bus transmitter v sup to dsixo on resistance (during idle) i out = -100 ma r ds(on) ? ? 10 ? output high voltage dsix0 (-15 ma i out 1.0 ma) dsiv oh 4.175 4.5 4.825 v output low voltage dsix0 (-15 ma i out 1.0 ma) dsiv ol 1.325 1.5 1.675 v output high-side current limit (5) i clh - 100 ? -200 ma output low-side current limit (5) i cll 110 ? 220 ma input leakage dsixo when dsixf is high and dsixs is low (0 v dsixo min (v sup = 16.5 v)) dsi ib - 200 ? 50 a bus receiver return current threshold i rh - 5.0 - 6.0 - 7.0 ma microcontroller interface logic input thresholds dsixs, dsixf v in(th) 1.10 ? 2.20 v output high voltage dsixr pin = -0.5 ma v oh 0.8 v dd ? v dd v output low voltage dsixr pin = 1.0 ma v ol 0.0 ? 0.2 v dd v internal pullup for dsixf i il -100 ? -10 a internal pulldown for dsixs i ih 10 ? 100 a notes 5. after 10 s settling time (assured by design).
analog integrated circuit device data 6 freescale semiconductor 33790 electrical characteristics dynamic electrical characteristics dynamic electrical characteristics table 4. dynamic electri cal characteristics characteristics noted under conditions 4.75 v v dd 5.25 v, 8.0 v v sup 25.0 v, -40 c t j 150 c unless otherwise noted. characteristic symbol min typ max unit microcontroller interface microcontroller signal cycle time t cyc 6.6 ? 1000 s microcontroller signal low time t cycl 2.0 ? 667 s microcontroller signal high time t cych 2.0 ? 667 s microcontroller signal duty cycle for logic zero dc lo 30 33 36 % microcontroller signal duty cycle for logic one dc hi 60.0 66.7 72.0 % microcontroller signal slew time (6) t slew ? ? 500 ns frame start to signal delay time t dly1 t cyc - 0.1 t cyc t cyc + 0.1 s signal end to frame end delay time t dly2 1.0 ? ? s rise time (6) t rise 0 ? 100 ns fall time (6) t fall 0 ? 100 ns bus transmitter idle to frame and frame to idle slew rate c 5.0 nf t slew (frame) 3.0 6.0 10.0 v/ s signal high to low and signal low to high slew rate c 5.0 nf t slew (signal) 3.0 4.5 8.0 v/ s data valid (v sup x = 25 v, c l 5.0 nf) dsixf, v in(th) to dsixo = 5.3 v dsixs, v in(th) to dsixo = 2.6 v dsixs, v in(th) to dsixo = 3.4 v dsixf, v in(th) to dsixo = 7.0 v t dvld1 t dvld2 t dvld3 t dvld4 2.44 0.25 0.25 0.25 ? ? ? ? 6.56 1.3 1.3 1.3 s bus receiver receiver delay time t drh : i = i rh to dsixr = 2.5 v t drl : i = i rh to dsixr = 2.5 v t drh t drl ? ? 400 400 750 750 ns notes 6. slew times and rise and fall times between 10% and 90% of output high and low levels.
analog integrated circuit device data freescale semiconductor 7 33790 electrical characteristics timing characteristics timing characteristics figure 4. timing characteristics 5.0 v 0 v 5.0 v 0 v 25 v 1.5 v 5.0 v 0 v 0 ma i rh dsixs dsixf dsixo dsixr v in(th) v in(th) 4.5 v i out t cyc t cyc h t dly2 t cyc l t rise t rise t fall t dly1 t dvld1 t slew (frame) t slew (signal) t dvld3 t dvld2 t drh t drl 5.0 v 7.0 v t dvld4 t cyc 3.0 v t tat dsiv oh (note (9) ) (note (8) ) note (7) notes 7. typical busin / busout logic thresholds (v thl ) from mc33793 datasheet. 8. t tat (turnaround time) is dependent upon wire length, bus loads, and slave re sponse characteristics. 9. dsixr stable on falling edge of dsixs or rising edge of dsixf.
analog integrated circuit device data 8 freescale semiconductor 33790 functional description introduction functional description introduction the 33790 is designed to provide the interface between logic and the dsi bus. it accepts signals with a typical 0 v to 5.0 v logic level to control the state of the bus output (idle level, logic high level, logic low level, and high impedance). it detects the curr ent drawn from the bus output during signaling and outputs a 0 v to 5.0 v logic level corresponding to the bus current being above (logic [1] out) the bus return logic [1] current or below (logic [0] out). the 33790 contains current limiting of the bus outputs as required by the dsi bus specification and thermal shutdown to protect itself from damage. two in dependent dsi bus outputs are provided by the ic. functional terminal description bus driver and receiver the wave-shaper converts the 0 v to 5.0 v logic inputs from dsixf (frame) and dsixs (signal) to a wave-shaped signal on the dsixo output, as shown in the timing diagrams in figure 2 , page 2 , and the truth table in table 5 . the bus current sense detects the current being drawn by the device(s) on the bus during signalling (dsixf = 0). if the current is above a set level, ds ixr will be high; otherwise, it is low. due to the variations in the turnaround time (t tat ) from slave devices and bus delays, dsixr should be sampled on the falling edge of dsixs and on the rising edge of dsixf (for the last return bit). the current for the idle state is from the supply connected to v sup and this supply should not be current limited below 250 ma per channel. during idle state, the voltage on the dsi bus will be very close to the v sup voltage. internal thermal shutdown circuitry and current limit individually protect the dsixo ou tputs from shorts to battery and ground. typically, the thermal shutdown occurs between 160 c and 170 c. if the junction temperature rises above this temperature, the internal tx lim bit is asserted, and the output drivers for dsixo are disabled by the thermal shutdown circuitry. the output drivers remain off until the junction temperature decreases below approximately 155 c, at which time the thermal shutdown circuitry turns off and the outputs are re-enabled. each dsixo output has a unique thermal sense and shutdown circuit, so a short on one channel does not affect the other channel. charge pump the charge pump uses on-board capacitors to step the input voltage up to the voltage needed to drive the on-board transmitter fets. a filter / stor age capacitor is connected to cpcap to hold the stepped-up voltage. input pullups and pulldowns internal current pullups are used on the dsixf pins and pulldowns on the dsixs pins. if these pins are left unconnected, their associated dsi bus will go to the unused (high impedance) state. table 5. dsi bus truth table dsixf dsixs tx lim dsixr dsixo 0 0 0 not defined low (1.5 v) 0 1 0 not defined high (4.5 v) 0 0 return data unchanged x 0 return data unchanged 1 0 0 0 high impedance 11 0 0idle v sup - 0.5 v x x 1 1 high impedance
analog integrated circuit device data freescale semiconductor 9 33790 typical applications functional terminal description typical applications the 33790 is intended for use in a dsi system. this device supplies the interface between st andard logic levels and the voltage and current requir ed for the dsi bus. two independent dsi busses are supported by this part. the 33790 does not form the timing for the dsi bus. this is done by logic either embedded in a microcontroller or by the mc68hc55, which uses spi commands and forms dsi protocol for communications over the dsi bus. the pins from the mc68hc55 are made to line up with the pins connecting to the 33790. this includes all the dsixf, dsixs, and dsixr pins. a capacitor attached to cpcap serves as a charge reservoir for the gate drive charge pump. this circuit creates a voltage that is higher than the source of the n-channel output transistor. this allows turning on of the transistor enough to prevent any significant voltage drop across it. the rest of charge pump electr onics are completely self- contained on the ic.
analog integrated circuit device data 10 freescale semiconductor 33790 packaging package dimensions packaging package dimensions for the most current package revision, visit www.freescale.com and perform a keyword search using the ?98a? listed below. dw suffix eg suffix (pb-free) 98asb42567b 16-pin soicw
analog integrated circuit device data freescale semiconductor 11 33790 revision history revision history revision date description of changes 7.0 5/2006 ? implemented revision history page ? converted to freescale format 8.0 11/2006 ? updated data sheet format ? removed peak package reflow temperature during reflow (solder reflow) parameter from maximum ratings on page 4 . added note with instructions to obtain this information from www.freescale.com. 9.0 11/2006 ? minor correction changes to figure 1 and ordering information 10.0 12/2006 ? restated note freescale?s package reflow capability meets pb-free requirements for jedec standard j-std-020c. for peak package reflow temperature and moisture sensitivity levels (msl), go to www.freescale.com, search by par t number [e.g. remove prefixes/suffixes and enter the core id to view all orderable parts. (i.e. mc33xxxd enter 33xxx), and review parametrics. on page 4
mc33790 rev 10.0 12/2006 information in this document is provided solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability ar ising out of the application or use of any product or circuit, and specifically discl aims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale se miconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the fa ilure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemni fy and hold freescale semiconductor and its officers, employees, subsidiaries, affili ates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc., 2006. all rights reserved. rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics of thei r non-rohs-compliant and/or non-pb-free counterparts. for further information, see http://www.freescale.com or contact your freescale sales representative. for information on freescale?s environmental products program, go to http:// www.freescale.com/epp . how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com

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